COMPUTER ARCHITECTURE MCQS
Which of the following is RISC processor?Intel 8086Pentium 4ARMCore i7C) ARMARM processors are based on RISC architecture (Reduced Instruction Set Computer).
Pipeline in computer architecture is used to:Increase latencyDecrease throughputIncrease instruction execution speedReduce clock speedC) Increase instruction execution speedPipelining improves CPU throughput by overlapping execution of instructions.
Cache memory is:Larger but slower than RAMFaster but smaller than RAMSame as virtual memorySecondary storageB) Faster but smaller than RAMCache provides very fast access to frequently used data.
Which type of control unit is faster?HardwiredMicroprogrammedCISCPipelinedA) HardwiredHardwired control is faster but less flexible compared to microprogrammed control.
Von Neumann architecture uses:Separate memory for data and instructionsSingle memory for data and instructionsNo memoryStack-based memoryB) Single memory for data and instructionsVon Neumann architecture stores both data and instructions in the same memory.
The control unit of a computer is responsible for:Storing dataDirecting data flow and instructionsPerforming arithmetic operationsDisplaying outputB) Directing data flow and instructionsThe control unit manages the execution of instructions by directing data flow between CPU components.
RISC architecture is characterized by:Complex instructions and fewer registersSimple instructions and more registersMicroprogrammed controlSlow pipeline performanceB) Simple instructions and more registersRISC (Reduced Instruction Set Computer) uses a small, highly optimized instruction set for efficiency.
The term “MAR” stands for:Memory Allocation RegisterMemory Address RegisterMachine Access RegisterMemory Arithmetic RegisterB) Memory Address RegisterMAR holds the address of memory location to be accessed for read/write operations.
Pipelining improves CPU performance by:Increasing clock speedReducing instruction setOverlapping execution of instructionsUsing more memoryC) Overlapping execution of instructionsPipelining executes multiple instructions simultaneously at different stages for faster throughput.
Which of the following is a hazard in pipelining?Data HazardMemory AllocationContext SwitchingFile ManagementA) Data HazardData hazards occur when an instruction depends on the result of a previous instruction still in the pipeline
CPI stands for:Clock Pulse IntervalCycles Per InstructionControl Process InstructionCurrent Program InstructionB) Cycles Per InstructionCPI measures the average number of clock cycles taken to execute an instruction.
Harvard Architecture is different from Von Neumann because:It uses single memory for code and dataIt uses separate memory for code and dataIt has no ALU It cannot be pipelinedB) It uses separate memory for code and dataHarvard architecture separates instruction and data memory for parallel access.
Which of the following is NOT a type of computer interrupt?Hardware InterruptSoftware InterruptSpurious InterruptCache InterruptD) Cache InterruptThere is no "cache interrupt"; interrupts are typically hardware or software generated.
Micro-operations are:CPU-level operations on data stored in registersAssembly instructionsMemory allocationsBus transfersA) CPU-level operations on data stored in registersMicro-operations perform simple tasks like data transfer or arithmetic inside the CPU.
Flynn’s taxonomy classifies computers based on:Memory sizeNumber of CPUsInstruction and data streamsOperating system typeC) Instruction and data streamsFlynn’s taxonomy divides computers into SISD, SIMD, MISD, and MIMD based on parallelism.